A Compact Gated-Synapse Model for Neuromorphic Circuits

This work reports a compact behavioral model for gated-synaptic memory. The is developed in Verilog-A easy integration into computer-aided design of neuromorphic circuits using emerging encompasses various forms gated synapses within single framework and not restricted to only type. theory the described detail along with full list default parameter settings. includes parameters, such as device's ideal set time, threshold voltage, general evolution conductance respect decay state, etc. Finally, model's validity shown via extensive simulation fitting experimentally reported data on published gated-synapses.